The present invention generally relates to technology mapping methods and storage media, and more particularly to a technology mapping method for automatically converting a logic circuit which does not depend on a specific circuit technology into a circuit which uses a specific cell library, and to a computer-readable storage medium which stores a program for causing a computer to carry out a technology mapping process using such a technology mapping method.
When designing a logic circuit, it is necessary to take into consideration various restricting conditions such as the circuit area, delay time and power consumption, in addition to the logic specifications. For this reason, the logic combining process which automatically designs the logic circuit normally employs a method which divides the process into a technology-independent combining process which is independent of the circuit technology and a technology-dependent combining process which is dependent on the circuit technology, and carries out the combining process according to respective partial targets.
The technology-dependent combining process is also called technology mapping, and is carried out when converting a technology-independent logic circuit into an actual circuit. Presently, the popularly used technology mapping employs a technique called a cell based design technique. When realizing a circuit by this cell based design technique, logic element parts which are prepared in advance, that is, cells, are combined to form the logic circuit.
The technology mapping which is conventionally reduced to practice is based on an algorithm called DAGON proposed in Kurt Keutzer, xe2x80x9cDAGON: Technology Binding and Local Optimizationxe2x80x9d, Proc. 24th ACM/IEEE Design Automation Conference, pp. 341-247, June 1987. This proposed algorithm called DAGON temporarily converts a target circuit which is to be designed into a circuit using basic cells such as 2-input NAND gates and NOT gates, and generates the actual circuit by assigning larger cells with respect to partial circuits which are made up of the NAND gates and the NOT gates.
A description will be given of an example of the design using the DAGON algorithm. First, with respect to each cell of a cell library, patterns made up of one or more 2-input NAND gates and/or one or more NOT gates and describing logical functions are prepared in advance. The decomposition of the cell is not uniquely determined, and various different decomposition patterns are conceivable. For this reason, all of the decomposition patterns are considered for each cell.
FIGS. 1 and 2 are diagrams showing examples of cells of the cell library and decomposition patterns of the cells. In FIG. 1, (a) shows a decomposition pattern of a cell NOT, (b) shows a decomposition pattern of a cell NAND2, (c) shows a decomposition pattern of a NAND3, (d) shows a decomposition pattern of a cell NAND4, (e) shows a decomposition pattern of the NAND4, (f) shows a decomposition pattern of a cell AOI21, (g) shows a decomposition pattern of a cell AOI22, and (h) shows a decomposition pattern of a cell AND2. In addition, in FIG. 2, (a) shows a decomposition pattern of a cell NOR2, (b) shows a decomposition pattern of a cell NOR3, (c) shows a decomposition pattern of a cell NOR4, (d) shows a decomposition pattern of the cell NOR4, (e) shows a decomposition pattern of a cell OAI21, (f) shows a decomposition pattern of a cell OAI22, and (g) shows a decomposition pattern of a cell AOR2. In FIG. 1, the cell NAND4 has two kinds of decomposition patterns as shown in (d) and (e). In FIG. 2, the cell NOR4 has two kinds of decomposition patterns as shown in (c) and (d).
If it is assumed for the sake of convenience that a target technology-independent logic circuit which is to be designed is formed by virtual AND gates, OR gates and NOT gates, the AND gate can be realized by use of 2-input NAND gates and NOT gates as shown in FIG. 3(a), and the OR gate can be realized by use of 2-input NAND gates and NOT gates as shown in FIG. 3(b). Accordingly, it is possible to easily convert an initial circuit into a circuit consisting solely of the 2-input NAND gates and the NOR gates. In this case, a plurality of decomposition patterns are conceivable, but only one decomposition pattern is normally considered since it is difficult to consider all of the decomposition patterns.
FIG. 4 shows an example of the initial circuit which is decomposed in the above described manner. With respect to the initial circuit shown in FIG. 4, it is possible to assign partial circuits as shown in FIG. 5. In FIG. 5, each partial circuit surrounded by a bold solid line is assigned with respect to one cell. However, such an assignment of the partial circuits with respect to the cells is not uniquely determined, and for example, it is possible to assign partial circuits as shown in FIG. 6 with respect to the initial circuit shown in FIG. 4. In FIG. 6, each partial circuit surrounded by a bold solid line is assigned with respect to one cell.
When assigning the partial circuits with respect to the cells, the technology mapping process selects a most desirable assignment by taking into consideration the restricting conditions and the target functions such as the circuit area, delay time and power consumption. Accordingly, the technology mapping process requires two stages of processes, namely, a matching process and a covering process. The matching process lists the cells which match the partial circuits of the initial circuit. In addition, the covering process generates the actual circuit by combining the matching cells. In this case, a match refers to a combination of the partial circuit surrounded by the bold solid line and the cell indicated beside the partial circuit in FIGS. 5 and 6. In the matching process, all possible matches are listed regardless of whether or not the match is obtained as a result.
With respect to the matching process, an algorithm called graph matching is proposed in R. L. Rudell, xe2x80x9cLogic Synthesis For VLSI Designxe2x80x9d, PhD Thesis, UCB/ERL M89/49, 1989.
FIG. 7 is a flow chart showing a typical matching process. In FIG. 7, a step S1 decides whether or not a non-tested node exists in the initial circuit, and the process ends if the decision result in the step S1 is NO. On the other hand, if the decision result in the step S1 is YES, a step S2 obtains one node and denotes this node by v. A step S3 decides whether or not a non-tested pattern exists, and the process returns to the step S1 if the decision result in the step S3 is NO. If the decision result in the step S3 is YES, a step S4 obtains one pattern and denotes this pattern by p. A step S5 obtains a match with respect to the pattern p at the node v, and the process returns to the step S3. The graph matching referred above is used in the process of the step S5.
Accordingly, when testing the matching of all of the patterns shown in FIGS. 1 and 2 with respect to an initial circuit shown in FIG. 17(a) which will be described later, the conventional matching process must successively carry out the matching with respect to all of the patterns with respect to all nodes 1, 2, 3, . . . of the initial circuit.
For the sake of convenience, a description will be given of a case where the matching of only one pattern is checked with respect to the initial circuit shown in FIG. 17(a) by the matching process shown in FIG. 7. In this case, a check is made to determine whether or not a pattern OAI21 shown in FIG. 17(b) matches with respect to each node of the initial circuit shown in FIG. 17(a). In FIG. 17(b), a1 through h1 indicate both nodes and corresponding input/output signal names, and these node names are unrelated to the node names shown in FIGS. 1 and 2.
(1) First, a check is made to determine whether or not a match having the node 1 as a root exists. In this case, the node 1 is an inverter, but the node a1 is a 2-input NAND gate, and no match exists.
(2) Next, a check is made to determine whether or not a match having a node as a root exists. In this case, both the node 2 and the node a1 are 2-input NAND gates, and the match exists.
There are two inputs to the 2-input NAND gate, and a check is first made to determine whether or not a node 3 and the node b1 match. In this case, both the node 3 and the node b1 are inverters, and the match exists.
Similarly, both a node 4 and the node c1 are inverters and a match exists, and both a node 5 and the node d1 are inverters and a match exists.
The two inputs e1 and g1 of the node d1 respectively match nodes 6 and 10, and the two inputs f1 and h1 of the nodes e1 and g1 respectively match nodes 7 and 11. Nodes 7 and 11 become termination nodes.
When a check is made to determine whether the remaining input i1 of the node a1 matches a node 14, a match exists unconditionally since the node i1 is a termination node.
As described above, all portions of the pattern OAI21 match, and the matching of the entire pattern is successful in this case. The termination nodes are determined so that the nodes f1 and 7 correspond, the nodes h1 and 11 correspond, and the nodes i1 and 14 correspond.
When a combination of the nodes b1 and 14 is tested with respect to the inputs of the node a1, a match exists because both the nodes b1 and 14 are inverters.
In addition, when a combination of the nodes c1 and 15 is tested with respect to the inputs of the node b1, a match exists because both the nodes c1 and 15 are inverters. Similarly, when a combination of the nodes d1 and 16 is tested, a match exists because both the nodes d1 and 16 are inverters.
The inputs e1 and g1 of the node d1 respectively match nodes 17 and 19, and the inputs f1 and h1 of the nodes d1 and e1 respectively match nodes 18 and 20. The nodes 18 and 20 become termination nodes.
Since the remaining input i1 of the node a1 matches the node 3, the node 3 also becomes a termination node.
As a result, another matching is obtained, and the correspondences of the termination nodes are such that the nodes f1 and 18 correspond, the nodes h1 and 20 correspond, and the nodes i1 and 3 correspond.
(3) Because the nodes 3 and 4 are inverters, no match exists with respect to the node a1.
(4) When the matching of the nodes 5 and a1 is tested, a match exists between the nodes 5 and a1 in this case.
When the matching of the input of the node 5 and the input of the node a1 is checked, a match exists between the nodes 6 and b1 because both the nodes 6 and b1 are inverters.
However, no match exists between the nodes 7 and c1, and as a result, it is concluded that no match exists between the nodes 6 and b1.
When the matching between the nodes 6 and i1 is checked, a match exists between the nodes 6 and i1.
When the matching of the remaining inputs of the node 5 is checked, a match exists between the nodes 10 and b1 because both the nodes 10 and b1 are inverters.
However, no match exists between the nodes 11 and c1, and as a result, it is concluded that no match exists between the nodes 10 and b1.
Because no match exists with respect to the inputs of the node 5, it is concluded that no match exists between the nodes 5 and a1.
The pattern matching is carried out with respect to all of the nodes of the initial circuit in the manner described above. Actually, the matching of not only one pattern with respect to the initial circuit is checked, but the matching of a plurality of patterns with respect to the initial circuit is checked.
In the covering process which is carried out in a stage next to the matching process, the matches obtained by the matching process are used as parts, and a combination of the matches is generated to cover the entire circuit as if tiles were being used to cover the entire circuit. In this state, an algorithm for minimizing the circuit area, an algorithm for minimizing the delay time and the like are proposed in R. L. Rudell, xe2x80x9cLogic Synthesis For VLSI Designxe2x80x9d, PhD Thesis, UCB/ERL M89/49, 1989.
In the actual program which carries out the technology mapping process, the matching process and the covering process described above are not clearly separated, and the covering process is carried out while obtaining the match by the matching process. But for the sake of convenience, the matching process and the covering process will be described separately, because attention is being drawn particularly to the matching process.
On the other hand, a technique called inverter chain heuristic has been proposed. According to the inverter chain heuristic technique, two inverters are inserted in series into a connecting line having no inverter, with respect to the initial circuit. As shown in FIG. 8, it is possible to find matches which could not be obtained by other techniques, and there is a possibility that a satisfactory circuit can be synthesized using the inverter chain heuristic technique. In FIG. 8, an inverter pair which is not surrounded by a bold solid line is removed from the final circuit.
As described above, there are cases where a plurality of patterns are required with respect to one cell, and in addition, there is a tendency for the number of required patterns to increase as the number of input signals of the cell increases. In a worst case, the required number of patterns is proportional to an exponential power of the number of input signals to the cell. In such a case, the cells of the cell library become complex and large scale, and there is a problem in that it takes an extremely long time to list all of the patterns and to search the matches with respect to all of the patterns.
Recently, there is a tendency for the number itself of the cells usable in the cell library to increase. For this reason, the required memory capacity and calculation time both increase considerably if the conventional simple matching algorithm is used, and there is a problem in that the processing speed deteriorates or the process itself becomes impossible to carry out.
Accordingly, it is a general object of the present invention to provide a novel and useful technology mapping method and storage medium, in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a technology mapping method and storage medium, which can carry out a matching process efficiently with respect to a cell library which has a tendency to become large scale and complex.
Still another object of the present invention is to provide a technology mapping method which automatically converts a logic circuit which does not depend on a specific circuit technology into a circuit which uses a specific cell library, using a computer, comprising an optimizing step of optimizing a pattern which is to be subjected to a matching process based on an inclusion relationship of structures of patterns with respect to each cell. According to the present invention, it is possible to carry out the matching process efficiently with respect to the cell library which has the tendency of becoming large scale and complex.
The optimizing step may omit the matching process with respect to a pattern which includes a pattern for which no match is obtained.
The optimizing step may define similar patterns which only differ by inverters provided at input and output sides thereof, and determine one representative pattern with respect to each group of the similar patterns, and the technology mapping method may further comprise a matching step of carrying out the matching process only with respect to the representative pattern.
The matching step may obtain a match with respect to the similar patterns within a group based on a conversion map which indicates how a match with respect to the representative pattern should be converted in order to obtain a match with respect to the similar patterns within the group to which the representative pattern belongs.
A further object of the present invention is to provide a computer-readable storage medium which stores a program for causing a computer to automatically convert a logic circuit which does not depend on a specific circuit technology into a circuit which uses a specific cell library, comprising optimizing means for causing the computer to optimize a pattern which is to be subjected to a matching process based on an inclusion relationship of structures of patterns with respect to each cell. According to the present invention, it is possible to carry out the matching process efficiently with respect to the cell library which has the tendency of becoming large scale and complex.
The optimizing means may cause the computer to omit the matching process with respect to a pattern which includes a pattern for which no match is obtained.
The optimizing means may cause the computer to define similar patterns which only differ by inverters provided at input and output sides thereof, and to determine one representative pattern with respect to each group of the similar patterns, and the computer-readable storage medium may further comprise matching means for causing the computer to carry out the matching process only with respect to the representative pattern.
The matching means may cause the computer to obtain a match with respect to the similar patterns within a group based on a conversion map which indicates how a match with respect to the representative pattern should be converted in order to obtain a match with respect to the similar patterns within the group to which the representative pattern belongs.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.